• Micron Technology PC100 memory module chip number MT48LC8M8A2
  •  DIMM 128MB SYNCH 100 MHz
  • One double sided 168 pin DIMM memory module unbuffered non-ECC
  • Limited lifetime warranty
  • Fully tested and working
General Description
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 
67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous interface 
(all signals are registered on the positive edge of the clock signal, CLK). Each of 
the x4’s 16,777,216-bit banks is organized as 4096 rows by 1024 columns by 4 bits. Each
of the x8’s 16,777,216-bit banks is organized as 4096 rows by 512 columns by 8 bits. Each 
of the x16’s 16,777,216-bit banks is organized as 4096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected 
location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command, which is then followed 
by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the 
bank; A[11:0] select the row). The address bits registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access. 
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function 
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence. 
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. 
This architecture is compatible with the 2n rule of prefetch architectures, but it also 
allows the column address to be changed on every clock cycle to achieve a highspeed, 
fully random access. Precharging one bank while accessing one of the other
three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-
access operation. 
The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh 
mode is provided, along with a power-saving, power-down mode. All inputs and outputs 
are LVTTL-compatible.
SDRAM devices offer substantial advances in DRAM operating performance, including 
the ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks to hide precharge 
time, and the capability to randomly change column addresses on each clock cycle during
a burst access.