Description
ADRV9009 RF Daughterboard ADRV9009-W/PCBZ Radio Card 75MHz to 6GHz For Ham Radio DIY Enthusiasts
Description:
ADRV9008/ADRV9009 evaluation and prototyping platform
For ADI provides a complete set of software and hardware tools for evaluation, prototyping, and reference design. The following table lists the available software and hardware tools.
ADRV9009-W/PCBZ is a radio card designed to demonstrate ADRV9009-a wider bandwidth, higher performance RF integrated transceiver. The radio card provides a single 2x2 transceiver platform for device evaluation and rapid prototyping of radio solutions. All the peripherals required for the operation of the radio card-including a high-efficiency only switching power supply solution, and a high-performance clock solution-have been installed on the circuit board. ADRV9009-W/PCBZ is a single-chip TDD solution for dual-channel receivers and dual-channel transmitters with integrated observation receivers.
ADRV9009-W/PCBZ can work in a wide tuning range from 75MHz to 6GHz, but the RF performance is corrected by the extremely wide bandwidth front-end matching. This board is mainly used for the software development team to conduct system research and provide various waveforms before the customized hardware is completed. The designer's purpose is to view the waveform, not to care about the performance of the last 1 dB or 1% EVM.
Chip Features:
- Dual transmitter
- Dual receivers
- Dual input shared observation receiver
- Maximum receiver bandwidth: 200 MHz
- Maximum tunable transmitter synthesis bandwidth: 450 MHz
- Maximum observation receiver bandwidth: 450 MHz
- Fully integrated fractional-N RF synthesizer
- Fully integrated clock synthesizer
- Multi-chip phase synchronization for RF LO and baseband clock
- JESD204B data path interface
- Tuning range: 75 MHz to 6000 MHz
Performance & Advantages:
The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.
The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.
In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.
The received signals are digitized with a set of four high dynamic range, continuous time Σ-Δ ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.
The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.
The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.
The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.
The high speed JESD204B interface supports up to 12.288Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.
The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).
Applications:
- 3G, 4G, and 5G TDD macrocell base stations
- TDD active antenna systems
- Massive multiple input, multiple output (MIMO)
- Phased array radar
- Electronic warfare
- Military communications
- Portable test equipment
Product Details:
- Completely in accordance with the official board file and BOM, strictly in accordance with the official production process (such as for Rogers board and three-level impedance, etc.), there is no difference between the performance and the official comparison.
- Can completely replace official products.
Package Included:
- 1 x RF Daughter Board
Description:
ADRV9008/ADRV9009 evaluation and prototyping platform
For ADI provides a complete set of software and hardware tools for evaluation, prototyping, and reference design. The following table lists the available software and hardware tools.
ADRV9009-W/PCBZ is a radio card designed to demonstrate ADRV9009-a wider bandwidth, higher performance RF integrated transceiver. The radio card provides a single 2x2 transceiver platform for device evaluation and rapid prototyping of radio solutions. All the peripherals required for the operation of the radio card-including a high-efficiency only switching power supply solution, and a high-performance clock solution-have been installed on the circuit board. ADRV9009-W/PCBZ is a single-chip TDD solution for dual-channel receivers and dual-channel transmitters with integrated observation receivers.
ADRV9009-W/PCBZ can work in a wide tuning range from 75MHz to 6GHz, but the RF performance is corrected by the extremely wide bandwidth front-end matching. This board is mainly used for the software development team to conduct system research and provide various waveforms before the customized hardware is completed. The designer's purpose is to view the waveform, not to care about the performance of the last 1 dB or 1% EVM.
Chip Features:
- Dual transmitter
- Dual receivers
- Dual input shared observation receiver
- Maximum receiver bandwidth: 200 MHz
- Maximum tunable transmitter synthesis bandwidth: 450 MHz
- Maximum observation receiver bandwidth: 450 MHz
- Fully integrated fractional-N RF synthesizer
- Fully integrated clock synthesizer
- Multi-chip phase synchronization for RF LO and baseband clock
- JESD204B data path interface
- Tuning range: 75 MHz to 6000 MHz
Performance & Advantages:
The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.
The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.
In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.
The received signals are digitized with a set of four high dynamic range, continuous time Σ-Δ ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.
The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.
The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.
The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.
The high speed JESD204B interface supports up to 12.288Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.
The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).
Applications:
- 3G, 4G, and 5G TDD macrocell base stations
- TDD active antenna systems
- Massive multiple input, multiple output (MIMO)
- Phased array radar
- Electronic warfare
- Military communications
- Portable test equipment
Product Details:
- Completely in accordance with the official board file and BOM, strictly in accordance with the official production process (such as for Rogers board and three-level impedance, etc.), there is no difference between the performance and the official comparison.
- Can completely replace official products.
Package Included:
- 1 x RF Daughter Board
Payment Terms
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3.Payment must be received within 7 business days of auction closing.
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2.All major credit cards are accepted through secure payment processor PayPal.
3.Payment must be received within 7 business days of auction closing.
4.We ship to your eBay or Paypal address. Please make sure your eBay and Paypal address is correct before you pay.
Shipping Terms
- For remote regions, we will charge your extra shipping costs. Usually it cost about 35USD-50USD. We will contact you after your payment. Thanks for your understanding.
Return Terms
1. If you receive defective item, please kindly notify us within 14 days. We will guide you the returning instruction for replacement or refund.
2. If you purchased in improper condition, please NOTE that the sipping and handling fee will not be refund, all return shipping fee should paid by the buyer unless item DOA.
3. We reserve the right to refuse any returns for objective reasons.
2. If you purchased in improper condition, please NOTE that the sipping and handling fee will not be refund, all return shipping fee should paid by the buyer unless item DOA.
3. We reserve the right to refuse any returns for objective reasons.
Custom Duties & Taxes
1. Import duties, taxes, and charges are not included in the item price or postage cost. These charges are the buyer's responsibility.
2. Avoiding some unnecessary trouble, please check with your country's customs office to inform us what we should declare its value before shipping.
2. Avoiding some unnecessary trouble, please check with your country's customs office to inform us what we should declare its value before shipping.
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2. If you are satisfied with the product you received, please kindly leave us a positive feedback and 5 star DSR. If there is any problem of your order, please feel free to contact us firstly, we are responsible and credible seller, will follow it for you asap.
