The Model 3655 is a single-width CAMAC module containing a 16-bit counter and eight 16-bit set-point registers that are compared with the counter. The comparisons produce output pulses, and any of them can be used to either stop or clear the counter. The comparisons also produce LAM status bits, which can be individually enabled to produce LAM requests. A flag bit determines whether the counter stops with the last output pulse or whether it is cleared to produce repeating sequences of timing pulses. In the former mode of operation, additional pulse sequences are initiated either by programmed command or by external signal or contact closure. The 3655 provides its own crystal clock, and the input frequency to the counter is software-controlled for any decade from one hertz to one megahertz. Input to the counter can also come from an external source. Two of the comparison scan set and clear the Dataway Inhibit. Numbers in the eight registers (or fewer, if less than eight pulse sources are required) must be stored in increasing numerical order for proper timing of utput pulses. Two control registers provide programmable control of the clock frequency (one hertz to one megahertz), the number of channels that generate a pulse (one to eight), the assertion of Dataway Inhibit, and whether to stop or recycle after the last pulse. The bit assignments in the registers are shown on the following page. Bits 1, 2, 3 = N, where clock frequency = 10NHz (N = 7 selects the external input) Bits 4, 5, 6 = P, where P + 1 = number of channels that generate a pulse Bits 7 = 1 to continuously cycle, 0 to cycle once and stop. All inputs and outputs appear on front-panel LEMO connectors as well as on the 36- pin P.C. connector at the rear of the module.

Features:

Eight independent outputs

Self-contained crystal clock

Provision for external clock

Option for high-true or low-true output pulses

LAM status bit associated with each output channel

8-bit LAM mask register

Clock variations from one hertz

Clock rate under software control

Ability to cycle through any number of channels from one to eight

Ability to control Dataway Inhibit

Ability to cycle once and stop or to continue cycling

Ability to start cycle by external signal or by internal command

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Condition:  

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