This document describes ValueRAM’s 512M x 72-bit 4GB

(4096MB) DDR3-1066 CL7 SDRAM (Synchronous DRAM)

registered w/parity, quad-rank memory module, based on thirtysix 128M x 8-bit DDR3-1066 FBGA components. The SPD is

programmed to JEDEC standard latency 1066Mhz timing of

7-7-7 at 1.5V. This 240-pin DIMM uses gold contact fingers and

requires +1.5V. The electrical and mechanical specifications

are as follows:

FEATURES

• JEDEC standard 1.5V ± 0.075V Power Supply

• VDDQ = 1.5V ± 0.075V

• 533MHz fCK for 1066Mb/sec/pin

• 8 independent internal bank

• Programmable CAS Latency: 6,7,8,9,10

• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock

• Programmable CAS Write Latency(CWL) = 6(DDR3-1066)

• 8-bit pre-fetch

• Burst Length: 8 (Interleave without any limit, sequential with

starting address “000” only), 4 with tCCD = 4 which does

not allow seamless read or write [either on the fly using A12

or MRS]

• Bi-directional Differential Data Strobe

• Internal(self) calibration : Internal self calibration through ZQ

pin (RZQ : 240 ohm ± 1%)

• On Die Termination using ODT pin

• On-DIMM thermal sensor (Grade B)

• Average Refresh Period 7.8us at lower than TCASE 85°C,

3.9us at 85°C < TCASE ≤ 95°C

• Asynchronous Reset

• PCB : Height 1.180” (30.00mm), double sided component