The PlayStation signaled Sony's rise to power in the video game industry. It received acclaim and sold strongly; in less than a decade, it became the first computer entertainment platform to ship over 100 million units. Its use of compact discs heralded the game industry's transition from cartridges. The PlayStation's success led to a line of successors, beginning with the PlayStation 2 in 2000. In the same year, Sony released a smaller and cheaper model, the PS one.

Central processing unit (CPU)

LSI CoreWare CW33300-based core
    MIPS R3000A-compatible 32-bit RISC CPU MIPS R3051 with 5 KB L1 cache, running at 33.8688 MHz.
    The microprocessor was manufactured by LSI Logic Corp. with technology licensed from SGI.
    Features:
        Initial feature size (process node) was 0.5 micron (500 nm).
        850k – 1M transistors[citation needed]
        Operating performance: 30 MIPS
        Bus bandwidth 132 MB/s
        One arithmetic/logic unit (ALU)
        One shifter
    CPU cache RAM:
        4 KB instruction cache
        1 KB data cache configured as a scratchpad

Geometry Transformation Engine (GTE)
    Coprocessor that resides inside the main CPU processor, giving it additional vector math instructions used for 3D graphics, lighting, geometry, polygon and coordinate transformations – GTE performs high-speed matrix multiplications.
    Operating performance: 66 MIPS
    Polygons per second (rendered in hardware):
        90,000 with texture mapping, lighting and Gouraud shading[citation needed]
        180,000 with texture mapping
        360,000 with flat shading

Motion Decoder (MDEC)
    Also residing within the main CPU, enables full screen, high quality FMV playback and is responsible for decompressing images and video into VRAM.
    Operating performance: 80 MIPS
    Documented device mode is to read three RLE-encoded 16×16 macroblocks, run IDCT and assemble a single 16×16 RGB macroblock.
    Output data may be transferred directly to GPU via DMA.
    It is possible to overwrite IDCT matrix and some additional parameters, however MDEC internal instruction set was never documented.
    It is directly connected to a CPU bus.

System Control Coprocessor (Cop0)
    This unit is part of the CPU. Has 16 32-bit control registers.
    Modified from the original R3000A cop0 architecture, with the addition of a few registers and functions.
    Controls memory management through virtual memory technique, system interrupts, exception handling, and breakpoints.

Memory
    2 MB main EDO DRAM
    Additional RAM is integrated with the GPU (including a 1 MB framebuffer) and SPU (512 KB), see below for details.
    Cache RAM for CPU core and CD-ROM. See the relevant sections for details.
    Flash RAM support through the use of memory cards, see below.
    BIOS stored on 512 KB ROM

Graphics processing unit (GPU)

32-bit Sony GPU (designed by Toshiba)
    Handles display of graphics, control of framebuffer, and drawing of polygons and textures
    Handles 2D graphics processing, in a similar manner to the 3D engine
    RAM:
        1 MB VRAM (later models contained SGRAM) for framebuffer
        2 KB texture cache (132 MB/s memory bus bandwidth, 32-bit wide)
        64 bytes FIFO buffer
    Features:
        Adjustable framebuffer (1024×512)
        Emulation of simultaneous backgrounds (to simulate parallax scrolling)
        Mask bit
        Texture window
        Dithering
        Clipping
        Alpha blending (4 per-texel alpha blending modes)
        Fog
        Framebuffer effects
        Transparency effects
        Render to texture
        Offscreen rendering
        Multipass rendering
        Flat or Gouraud shading and texture mapping
        No line restriction
        Colored light sourcing
    Resolutions:
        Progressive: 256×224 to 640×240 pixels
        Interlaced: 256×448 to 640×480 pixels
    Colors:
        Maximum color depth of 16,777,216 colors (24-bit true color)
        57,344 (256×224) to 153,600 (640×240) colors on screen
        Unlimited color lookup tables (CLUTs)
        32 levels of transparency
        All calculations are performed to 24 bit accuracy
    Texture mapping color mode:
        Mode 4: 4-bit CLUT (16 colors)
        Mode 8: 8-bit CLUT (256 colors)
        Mode 15: 15-bit direct (32,768 colors)
        Mode 24: 24-bit (16,777,216 colors)
    Sprite engine
        1024×512 framebuffer, 8×8 and 16×16 sprite sizes, bitmap objects
        Up to 4,000 sprites on screen (at 8×8 sprite size), scaling and rotation
        256×256 maximum sprite size
    Special sprite effects:
        Rotation
        Scaling up/down
        Warping
        Transparency
        Fading
        Priority
        Vertical and horizontal line scroll

Sound processing unit (SPU)

16-bit Sony SPU
    Supports ADPCM sources with up to 24 channels
    Sampling rate of up to 44.1 kHz
    512 KB RAM
    PCM audio source
    Supports MIDI sequencing
    Digital effects include:
        Pitch modulation
        Envelope
        Looping
        Digital reverb

I/O system and connectivity

CD-ROM drive
    660 MB maximum storage capacity, double speed (CLV) CD-ROM drive
    2×, with a maximum data throughput of 300 KB/s (double speed), 150 KB/s (normal)
    32 KB data buffer
    XA Mode 2 compliant
    Audio CD play
    CD-DA (CD-Digital Audio)
    Rated for 70,000 seek operations

Two control pads via connectors
    Expandable with multitap connector

Backup flash RAM support
    Two removable cards
    Each card has 128 KB flash memory
    OS support for File Save, Retrieve and Remove
    Some games (like "Music 2000") can use Memory Cards as main RAM, to store data for real time processing, bypassing the 2MB RAM limit.

Video and audio connectivity
    AV Multi Out (Composite video, S-Video, RGBS)
    RCA Composite video and Stereo out (SCPH-100x to 5000 only)
    RFU (SCPH-112X) DC out (SCPH-100x to 5000 only)
    S-Video out (SCPH-1000 only)

Serial and parallel ports
    Serial I/O (used for PlayStation Link Cable SCPH-100x to 900x only)
    Parallel I/O (N/A) SCPH-100x to 750x only)

Power input
    120 V AC (NTSC-U/C)