Description
PCIE Bus Interface Chip CH368 Development Board Evaluation Board Learning Board PCIe Bus to 32Bit Local Bus
Description:
CH368 is a universal interface chip that connects to PCI-Express bus, supports I/O port mapping, memory mapping, extended ROM and interrupts. CH368 converts high-speed PCIE bus into an easy-to-use 32-bit or 8-bit active parallel interface which similar to ISA bus. It can be used for making low-cost PCIE bus-based computer cards, and upgrade to PCIE card from ISA or PCI bus based. Compared with other bus, PCIE is faster, real-time, better on control, so CH368 is suitable for high-speed real-time I/O control card, communication interface card, data acquisition card and so on. The figure below shows is application block diagram.
Features:
- Provides 8-bit or 32-bit active parallel bus based on PCIE bus.
- Provides 32-bit passive parallel interface, can be connected to other CPU or MCU bus, supports BusMaster/ DMA.
- Supports I/O read and write, automatic allocation of I/O base, supports up to 232 bytes of I/O port.
- Supports memory read and write, supports memory prefetch, direct mapping supports memory SRAM which capacity is 32KB.
- Read and write pulse width from 30nS to 450nS optional, 32-bit memory burst block access speed up to 50MB per second.
- Supports request input of level interrupt or edge interrupt, supports interrupt sharing.
- Supports flash expansion ROM boot without hard disk, provide extended ROM application subroutine library BRM.
- Provides high-speed 3-wire or 4-wire SPI serial host interface.
- Provides two-wire serial master interface, can hang serial EEPROM similar with 24C0X to store non-volatile data.
- Supports that can be set for device ID (Vendor ID, Device ID, Class Code, etc.) of PCI board in EEPROM.
- Built-in 2uS to 8mS hardware timing unit as delay reference for software operation.
- Driver for Windows 98/Me/2000/XP/Vista/7/8/8.1/10/SERVER 2003/2008/2012/2016 and Linux, provide application API through the DLL.
- 3.3V supply voltage, I/O pin supports 5V withstand voltage, supports low power sleep mode.
- LQFP-100 lead-free package, RoHS compliant.
Package:
Package Included:
- 1 x Board
The development board can demonstrate the functions:
IO read and write, MEM memory read and write (requires external MEM), I2C memory (24C02) read and write, SPI interface FLASH operation, CH368 configuration space read and write, interrupt operation, custom PCIe-ID function, and pulse width setting.
Description:
CH368 is a universal interface chip that connects to PCI-Express bus, supports I/O port mapping, memory mapping, extended ROM and interrupts. CH368 converts high-speed PCIE bus into an easy-to-use 32-bit or 8-bit active parallel interface which similar to ISA bus. It can be used for making low-cost PCIE bus-based computer cards, and upgrade to PCIE card from ISA or PCI bus based. Compared with other bus, PCIE is faster, real-time, better on control, so CH368 is suitable for high-speed real-time I/O control card, communication interface card, data acquisition card and so on. The figure below shows is application block diagram.
Features:
- Provides 8-bit or 32-bit active parallel bus based on PCIE bus.
- Provides 32-bit passive parallel interface, can be connected to other CPU or MCU bus, supports BusMaster/ DMA.
- Supports I/O read and write, automatic allocation of I/O base, supports up to 232 bytes of I/O port.
- Supports memory read and write, supports memory prefetch, direct mapping supports memory SRAM which capacity is 32KB.
- Read and write pulse width from 30nS to 450nS optional, 32-bit memory burst block access speed up to 50MB per second.
- Supports request input of level interrupt or edge interrupt, supports interrupt sharing.
- Supports flash expansion ROM boot without hard disk, provide extended ROM application subroutine library BRM.
- Provides high-speed 3-wire or 4-wire SPI serial host interface.
- Provides two-wire serial master interface, can hang serial EEPROM similar with 24C0X to store non-volatile data.
- Supports that can be set for device ID (Vendor ID, Device ID, Class Code, etc.) of PCI board in EEPROM.
- Built-in 2uS to 8mS hardware timing unit as delay reference for software operation.
- Driver for Windows 98/Me/2000/XP/Vista/7/8/8.1/10/SERVER 2003/2008/2012/2016 and Linux, provide application API through the DLL.
- 3.3V supply voltage, I/O pin supports 5V withstand voltage, supports low power sleep mode.
- LQFP-100 lead-free package, RoHS compliant.
Package:
Package Included:
- 1 x Board
The development board can demonstrate the functions:
IO read and write, MEM memory read and write (requires external MEM), I2C memory (24C02) read and write, SPI interface FLASH operation, CH368 configuration space read and write, interrupt operation, custom PCIe-ID function, and pulse width setting.
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3.Payment must be received within 7 business days of auction closing.
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3. We reserve the right to refuse any returns for objective reasons.
2. If you purchased in improper condition, please NOTE that the sipping and handling fee will not be refund, all return shipping fee should paid by the buyer unless item DOA.
3. We reserve the right to refuse any returns for objective reasons.
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Am 19.08.2022 hat der Verkäufer die folgenden Angaben hinzugefügt: