MC68000P8, Motorola 68000-CPU mit 8 MHz, 68k
Topzustand, getestet, einwandfrei
Ich biete hier eines der begehrtesten Ersatzteile aus dem Bereich des Retrocomputings an, die CPU 68000 von Motorola (bzw. einem Lizenznehmer), die so wie sie hier ist in diversen Amiga und Atari-Modellen verbaut ist, aber auch in einigen Macs, SUN-Workstations und noch einigen weiteren Exoten Verwendung fand. Auch fuer Sammler von zeitgenoessischen CPUs ideal, da die CPU sowohl optisch als auch technisch einwandfrei ist. Geboten wird auf einen Chip.
Die CPU ist getestet und laeuft einwandfrei.
For foreign bidders: If you have any questions, just send me a message. You are bidding on a full tested an working CPU MC68000 from Motorola (or licensee). Ideal replacement for your Amiga, Atari, SUN-Workstation or vintage Mac.
Einige Detailinfos zur 68000-Familie (nach Wikipedia):
Der Motorola 68000 ist ein 1979 eingeführter CISC-Prozessor aus der 68000er-Familie von Motorola. Er besitzt intern 32-Bit-Register, einen mit 32 Bit adressierten linearen Adressraum, davon 24 Bit extern verfügbar, acht 32-Bit-Datenregister, neun 32-Bit-Adressregister, ein 16-Bit-Statusregister sowie einen 16-Bit-Datenbus. Eine Variante ist der Motorola 68008, bei dem der Datenbus auf 8 Bit sowie der Adressbus auf 20 Bit in der DIP-Version (bzw 22 Bit in der PLCC-Version) reduziert sind. Als verbesserte Version kam der Motorola 68010 auf den Markt, der um Fehler bereinigt wurde und verbesserte Unterstützung von virtuellem Speicher bietet. Ein 68010 mit erweitertem Adressbus von 31 Bit wurde als Motorola 68012 angeboten. Später folgten noch der 68020, 68030, 68040 und 68060.
Die Bezeichnung 68000 kommt laut einer modernen Legende von der Anzahl Transistoren, die der Prozessor besitzt. Tatsächlich ist es jedoch die logische Fortsetzung der Typbezeichnung der älteren 8-Bit-Motorola-Prozessorfamilie Motorola 6800. Die Architektur der 68000-Familie basiert auf Mainframes, wie z. B. IBM360 sowie der LSI11/PDP11 von Digital Equipment, aber mit einem linearen Adressbereich, auf den ohne Verfahren wie Multiplexing, Segmentierung oder Paging direkt zugegriffen werden kann.
Der 68000er (auch 68k genannt) mit 8 MHz Taktfrequenz kam im 64-poligen DIL-Gehäuse (siehe Bild) auf den Markt. Mit dem Übergang zu höheren Taktraten wurden dann ab 16 MHz nur noch 68-polige PLCC-Gehäuse verwendet.
Architektur und Befehlssatz
Die Prozessoren der 68000-Familie zeichnen sich durch die große Anzahl der Register und einen weitgehend orthogonalen Befehlssatz aus, d. h. fast alle Maschinenbefehle lassen sich mit allen Adressierungsarten verwenden. Dieser orthogonale Befehlssatz ist folgendermaßen aufgebaut:
BEFEHL.s ,
Die 68000-Familie ist eine sogenannte Zwei-Adress-Maschine, wobei bei den meisten Befehlen eine variable Datenbreite mit .s = {B,W,L} verwendet werden kann (entspricht 8, 16 oder 32 Bit) und für die beiden Quell- und Ziel-Operanden bzw. eine der 68000-Adressierungsarten eingesetzt werden kann:
Schreibweise
Beschreibung
Beispiel
Dn
Datenregister direkt
CLR.B D0
An
Adressregister direkt
MOVEA.W A0,A1
(An)
Adressregister indirekt
CLR.B (A0)
(An)+
Adressregister indirekt mit Postinkrement
CLR.B (A0)+
-(An)
Adressregister indirekt mit Predekrement
CLR.B -(A0)
d16(An)
Adressregister indirekt mit 16 Bit Offset
CLR.B 255(A0)
d8(An,Ri.s)
Adressreg. ind. mit 8 Bit Offset und Indexregister
CLR.B $44(A0,D0.L)
d16(PC)
PC-relativ mit 16 Bit Offset
CLR.B 22(PC)
d8(PC,Ri.s)
PC relativ mit 8 Bit Offset und Indexreg.
CLR.B 10(PC,A1.W)
#xxxxxxxx
Konstante (Immediate)
MOVEQ.L #15,D0
$xxxx
Speicherdirekt mit 16-Bit-Adresse (Absolute Short)
CLR.B $8000
$xxxxxxxx
Speicherdirekt mit 32-Bit-Adresse (Absolute Long)
CLR.B $11008000
oder die komplexen MC68020/30/40/60-Adressierungsarten:
Schreibweise
Beschreibung
Beispiel
(dis1,An,Ri.s*scl)
Adressreg. indirekt mit 16-/32-Bit Offset
MOVE.B ($12345678,A1,A2.L*2),D0
([dis1,An],Ri.s*scl,dis2)
Doppelt indirekt mit Post-Index
MOVE.W ([5,A2],D0.W,$23456),D1
([dis1,An,Ri.s*scl],dis2)
Doppelt indirekt mit Pre-Index
MOVE.W ([5,A2,D0.W],$23456),D1
(dis1,PC,Ri.s*scl)
PC-indirekt mit 16- oder 32-Bit Offset
JSR (WEITER,PC)
([dis1,PC],Ri.s*scl,dis2)
PC-relativ,doppelt ind m. Post-Index
JSR ([SPRUNG,PC],D1,2)
([dis1,PC,Ri.s*scl],dis2)
PC-relativ,doppelt ind. m. Pre-Index
MOVE.L ([PARAMETER,PC,D1.W],4),D1
Der 68000 hat nur eine 16-Bit-ALU und auch einen 16-Bit-Befehlssatz, der aber sowohl mit 8-, 16- als auch 32-Bit-Datentypen umgehen kann (32-Bit-Architektur). Der MC68020/030/040/060 dagegen hat eine 32-Bit-ALU.
Beispiel für ein typisches M68000 Kommando:
JSR (Jump to subroutine)
Befehlsformat 0100 1110 10mm mrrr
Das Kommando (Opcode) ist 16 Bit breit. Drei Bits (m) werden für den Adressierungsmodus verwendet, drei weitere Bits für das benutzte (r) Register bzw. eine Distanzadresse (displacement).
0100 1110 1011 1010 wird so zu JSR (d16,PC). Da hier die PC-relative Adressierung mit Distanzadresse (displacement) zur Anwendung kommt, wird das folgende Wort als vorzeichenbehaftete relative Adresse (displacement) verwendet. Andere Kommandos wie MOVEQ #n,Dx sind sogar vollständig in 16 Bit kodiert.
Die Fähigkeit des 68000, bei fast allen Kommandos auch 32 Bit breite Adressen und Daten anzugeben (die dann natürlich bei einem 16-Bit-Bus in mehreren Zyklen gelesen werden mussten), vereinfachte die Softwareentwicklung ungemein, da es sich quasi um eine 32-Bit-Architektur handelte.
Es ergeben sich nicht wie z. B. beim Intel 8086 Probleme, Datensätze über 64 KiB Größe zu adressieren. Wegen der 16-Bit-ALU und des 16-Bit-Datenbusses wird der 68000 oft 16-Bit-Prozessor genannt, er führt jedoch klaglos 32-Bit-Software aus. Wegen der 16-Bit-ALU kostet z. B. eine 32-Bit-Addition die doppelte Zeit. Der Schaltkreis zur Generierung von Adressen hat jedoch volle 32 Bit, so dass z. B. das Durchsuchen eines Textes mit 8 Bit breiten Zeichen nicht langsamer ist, als von einem reinen 16-Bitter zu erwarten wäre. Zudem kann der Text ohne Modifikation des Programms länger als 64 KiB sein. 68000-Software ist 32-Bit-Software.
Der Inhalt der oberen 8 Bit eines Adressregisters wird vom 68000 beim Speicherzugriff ignoriert. Dadurch ist es möglich, diese Bits frei zu nutzen, beispielsweise für Meta-Informationen zu einem Zeiger (pointer). Bei späteren Prozessor-Generationen aus der 68000-Familie mit 32 Bit externem Adressbus führt dies offensichtlich zu Problemen. Da diese Art der Programmierung aber auf den frühen Macintosh-Rechnern sehr verbreitet war, hatten spätere Macintosh-Versionen mit 68020-Prozessor ohne Memory Management Unit (MMU) einen speziellen Baustein, genannt Address Management Unit (AMU), anstelle der MMU, der die oberen 8 Bit von Adressen optional ausmaskierte, um alte Software in einem 24-Bit-Kompatibilitätsmodus verwenden zu können. Als Prozessor mit Nanocode und Microcode ist der 68000 gewissermaßen auf Hardwareebene durch den Hersteller programmierbar. Das führte zu so interessanten Varianten wie dem 68000-360, der direkt auf dem Chip eine abgespeckte Fassung des IBM-System/360-Befehlssatzes ausführen konnte und für ein kleines 360-Modell von IBM benutzt wurde.
Außerdem ermöglichte dies einen einfachen Weg, um Varianten des Chips zu erzeugen. Die erste davon war der 68008, bei dem nur der Nanocode so verändert wurde, dass der Datenbus nur noch mit 8 Bit Breite angesprochen wurde. Eine weitere Variante war der 68010, der wesentlich besser mit virtuellem Speicher betrieben werden konnte und zudem noch einige Detailverbesserungen aufwies. Ein Ableger des 68010 war der nicht lange verfügbare 68012, der mehr Adressleitungen für größere Speicher (bis zu 2 GiB) zur Verfügung stellte. Später wurden Varianten meist direkt von der ursprünglichen CPU abgeleitet, wie z. B. der 68EC020 vom 68020 (24 statt 32 Adressleitungen) – oder der 68EC040 und der 68LC040 vom 68040 (es fehlten dann entweder die FPU oder die MMU). Ab dem 68020 wurden Schritt für Schritt auch erste 64-Bit-Befehle integriert (für einfache Multiplikationen).
Über drei binär kodierte Interruptleitungen können Interrupts mit sieben unterschiedlichen Prioritäten ausgelöst werden, davon ist die höchste nicht maskierbar. Zusammen mit entsprechenden Peripheriebausteinen sind bis zu 256 vektorisierte Interrupts möglich.
Der Prozessor enthält ferner Steuerleitungen, die signalisieren, ob als Nächstes ein Programmbefehl oder ein Datum geholt wird. Dies ermöglicht zwar den Aufbau von Rechnern mit getrenntem Speicher für Programme und Daten; eine Harvard-Architektur ist aber nicht möglich, da die dazu notwendigen getrennten Busse für Programme und Daten hier nicht vorhanden sind.
Verwendung
Bereits zu Beginn der 1980er Jahre fand die CPU, dank optionaler MMU, ihren Weg in die Unix-Welt. Sie wurde in hohen Stückzahlen in die Workstations von Apollo Computer (Apollo), HP (HP 9000-300) und Sun (Sun-1) oder auch von Digital Equipment Corporation (Vax 100) und SGI verbaut.
Mitte der 1980er Jahre folgten dann Personal- und Home-Computer, der erste war Lisa von Apple, die schon bald vom Macintosh (Mac) abgelöst wurde. Er wurde auch im Commodore Amiga, im Atari ST und Sinclair QL (68008) verbaut.
Ende der 1980er und Anfang der 1990er fand er sich dann in Spielkonsolen wie dem Sega Mega Drive oder dem Neo Geo. Auch in Schachcomputern (wie z. B. im Fidelity Mach IV als 68020 mit 20 MHz und Mephisto Amsterdam als 68000 mit 12 MHz) wurde der Prozessor verwendet.
In Taschenrechnern von Texas Instruments wie dem TI-89 (Titanium), TI-92 (Plus) und Voyage 200 findet er heute noch Anwendung. Im Airbus A320 steuert er den Elevator Aileron Computer (ELAC), der Teil des Flugsteuerungs-Systems ist.
Das Haupteinsatzgebiet des Prozessors waren und sind Steuerungsrechner in der Industrie, meist mit einem Echtzeitbetriebssystem wie OS-9 oder pSOS, Nucleus oder Linux68k, wobei Letzteres kein Echtzeitbetriebssystem im eigentlichen Sinne ist. Dieser Einsatz und die große Verbreitung waren nicht zuletzt dank der guten Interruptarchitektur und in der Kombination mit dem VMEbus möglich. In hoher Stückzahl fand sich dieser Prozessor auch in Laserdruckern. Zusätzlich wurde er auf LAN-Karten (Schneider und Koch) und auf SCSI-Controllern (DPD), aber auch in Modems (Zyxel) verwendet. Auch die Automobilindustrie - vornehmlich (Motor-)Steuergeräte - bevorzugte bis zum Erscheinen des PowerPC den Einsatz der MC683xx-Controller-Familie.
Die Hochleistungsmodelle der 68000-Familie sind der 68040 und 68060 (bis 66 bzw. 75 MHz). Da Apple nach dem 68040 auf PowerPC-CPUs wechselte, wurde der 68060 nur noch in Erweiterungskarten für den Amiga und den Atari Falcon 030 (CT60) sowie für spezielle Anwendungen (z. B. in eingebetteten Systemen wie in BMW-Modellen der 1990er Jahre oder hochleistungsfähigen Schachcomputern) verwendet.
Mittlerweile ist der eigentliche 68000 praktisch verschwunden, wird aber noch in Wahlcomputern der Firma Nedap eingesetzt. Motorola (heute Freescale) fertigt eine Vielzahl von Mikrocontrollern, die vom 68000 abstammen. Die Motorola-Coldfire-Familie (auf 68k basierende Entwicklung) ist weiterhin im Bereich eingebetteter Systeme sehr beliebt und geht bis zum V5 mit 400 MHz, der in HP-Laserdruckern Verwendung findet. Die DragonBall-Ableger wurden in den Einsteigermodellen der Palm PDAs verwendet und sind in einfachen Handys verbreitet.
Ein prominentes Beispiel für ein Coldfire-basiertes (Amiga-inspiriertes) System war die Metabox-1000-SetTopBox, die allerdings nie auf den Markt gekommen ist.
Weitere Komponenten
Die Prozessoren 68020, 68030, 68040 und 68060 hatten bereits Funktionen integriert, die heutzutage als „Novum“ z. B. bei ARM herausgestellt werden. Dazu gehören:
* interne Harvard-Architektur
* Branch Caches / Prediction
* Barrel-Shifter
* Pipelining / Prefetch
* User / Supervisor Mode (auch Protected Mode oder Kernel Mode genannt)
Andere wesentliche Errungenschaften beziehen sich auf die Embedded Controller (Single-Chip) der M68000-Familie, der M683xx-Familie. Hierzu gehören z. B. der MC68332, MC68360, MC68376. Diese Familie waren wegweisend mit folgenden Funktionen:
* BDM (Background Debug Mode), heute Nexus
* Dual Core (wobei die zweite CPU als intelligenter Peripheriecontroller eingesetzt wurde, z. B. beim
MC68332 als TPU – Timer Processing Unit oder beim
MC68360 als CPM – Communications-Processor-Module bzw. QUICC (Quad Integrated Communication Controller). Dieser Controller erlaubte das Verarbeiten aller möglichen seriellen Protokolle. Dies ist der Vorgänger vom bekannten Power QUICC der Power Architecture Familie.
The Motorola 68000 ("'sixty-eight-thousand'"; also called the Motorola 68K, "sixty-eight-kay") is a 16/32-bit[1] CISC microprocessor core designed and marketed by Motorola Semiconductor Products Sector (now Freescale Semiconductor). Introduced in 1979 with HMOS technology as the first member of the successful 32-bit m68k family of microprocessors, it is generally software forward compatible with the rest of the line despite being limited to a 16-bit wide external bus. After 30 years in production, the 68000 architecture is still in use.
History
The 68000 grew out of the MACSS (Motorola Advanced Computer System on Silicon) project, begun in 1976 to develop an entirely new architecture without backward compatibility. It would be a higher-power sibling complementing the existing 8-bit 6800 line rather than a compatible successor. In the end, the 68000 did retain a bus protocol compatibility mode for existing 6800 peripheral devices, and a version with an 8-bit data bus was produced. However, the designers mainly focused on the future, or forward compatibility, which gave the M68K platform a head start against later 32-bit instruction set architectures. For instance, the CPU registers are 32 bits wide, though few self-contained structures in the processor itself operate on 32 bits at a time. The MACSS team drew heavily on the influence of minicomputer processor design, such as the PDP-11 and VAX systems, which were similarly microcoded.
In the mid 1970s, the 8-bit microprocessor manufacturers raced to introduce the 16-bit generation. National Semiconductor had been first with its IMP-16 and PACE processors in 1973-1975, but these had issues with speed. The Intel 8086 in 1977 quickly gained popularity. The decision to leapfrog the competition and introduce a hybrid 16/32-bit design was necessary, and Motorola turned it into a coherent mission. Arriving late to the 16-bit arena afforded the new processor more transistors (roughly 40 000 active versus 20 000 active in the 8086), 32-bit macroinstructions, and acclaimed general ease of use.
The original MC68000 was fabricated using an HMOS process with a 3.5-micron feature size. Formally introduced in September 1979,[2] Initial samples were released in February 1980, with production chips available over the counter in November.[3] Initial speed grades were 4, 6, and 8 MHz. 10 MHz chips became available during 1981[citation needed], and 12.5 MHz chips by June 1982.[3] The 16.67 MHz "12F" version of the MC68000, the fastest version of the original HMOS chip, was not produced until the late 1980s. Tom Gunter, retired Corporate Vice President at Motorola, is known as the "Father of the 68000."
The 68000 became the dominant CPU for Unix based workstations including Sun workstations and Apollo/Domain workstations, and also was used for mass-market computers such as the Apple Lisa, Macintosh, Amiga, and Atari ST. The 68000 was used in Microsoft Xenix systems as well as a prototype NetWare Unix based Server (after the MC6800 series was not found to be powerful enough and before the move to Intel 8X086 processors). The 68000 was used in the first generation of desktop laser printers including the original Apple Inc. LaserWriter and the HP LaserJet. In 1982, the 68000 received an update to its ISA allowing it to support virtual memory and to conform to the Popek and Goldberg virtualization requirements. The updated chip was called the 68010. A further extended version which exposed 31 bits of the address bus was also produced, in small quantities, as the 68012.
To support lower-cost systems and control applications with smaller memory sizes, Motorola introduced the 8-bit compatible MC68008, also in 1982. This was a 68000 with an 8-bit data bus and a smaller (20 bit) address bus. After 1982, Motorola devoted more attention to the 68020 and 88000 projects.
Second-sourcing
Several other companies were second-source manufacturers of the HMOS 68000. These included Hitachi (HD68000), who shrank the feature size to 2.7-microns for their 12.5 MHz version,[3] Mostek (MK68000), Rockwell (R68000), Signetics (SCN68000), Thomson/SGS-Thomson (originally EF68000 and later TS68000), and Toshiba (TMP68000). Toshiba was also a second-source maker of the CMOS 68HC000 (TMP68HC000).
CMOS versions
The 68HC000, the first CMOS version of the 68000, was designed by Hitachi and jointly introduced in 1985.[4] Motorola's version was called the MC68HC000, while Hitachi's was the HD68HC000. The 68HC000 was eventually offered at speeds of 8-20 MHz. Except for using CMOS circuitry, it behaved identically to the HMOS MC68000, but the change to CMOS greatly reduced its power consumption. The original HMOS MC68000 consumed around 1.35 watts at an ambient temperature of 25 °C, regardless of clock speed, while the MC68HC000 consumed only 0.13 watts at 8 MHz and 0.38 watts at 20 MHz. (Unlike CMOS circuits, HMOS still draws power when idle, so power consumption varies little with clock rate.) Apple selected the 68HC000 for use in the Macintosh Portable.
Motorola replaced the MC68008 with the MC68HC001 in 1990.[5] This chip resembled the 68HC000 in most respects, but its data bus could operate in either 16-bit or 8-bit mode, depending on the value of an input pin at reset. Thus, like the 68008, it could be used in systems with cheaper 8-bit memories.
The later evolution of the 68000 focused on more modern embedded control applications and on-chip peripherals. The 68EC000 chip and SCM68000 core expanded the address bus to 32 bits, removed the M6800 peripheral bus, and excluded the MOVE from SR instruction from user mode programs.[6] In 1996, Motorola updated the standalone core with fully static circuitry drawing only 2 µW in low-power mode, calling it the MC68SEC000.
Motorola ceased production of the HMOS MC68000 and MC68008 in 1996,[8] but its spin-off company, Freescale Semiconductor, is still producing the MC68HC000, MC68HC001, MC68EC000, and MC68SEC000, as well as the MC68302 and MC68306 microcontrollers and later versions of the DragonBall family. The 68000's architectural descendants, the 680x0, CPU32, and Coldfire families, are also still in production.
As a microcontroller core
After being succeeded by "true" 32-bit microprocessors, the 68000 was used as the core of many microcontrollers. In 1989, Motorola introduced the MC68302 communications processor.
Applications
At its introduction, the 68000 was first used in high-priced systems, including multiuser microcomputers like the WICAT 150 [3], early Alpha Microsystems computers, Sage II / IV, Tandy TRS-80 Model 16, and Fortune 32:16; single-user workstations such as Hewlett-Packard's HP 9000 Series 200 systems, the first Apollo/Domain systems, Sun Microsystems' Sun-1, and the Corvus Concept; and graphics terminals like Digital Equipment Corporation's VAXstation 100 and Silicon Graphics' IRIS 1000 and 1200. Unix systems rapidly moved to the more capable later generations of the 68k line, which remained popular in that market throughout the 1980s.
By the mid-1980s, falling production cost made the 68000 viable for use in personal and home computers, starting with the Apple Lisa and Macintosh, and followed by the Commodore Amiga, Atari ST, and Sharp X68000. The 68008, on the other hand, was only used in a few home computer systems. The Sinclair QL (though the QL was a sister machine to the ICL One Per Desk, which also used a 68008) was the most commercially important. Helix Systems (in Missouri, United States) designed an extension to the SWTPC SS-50 bus, the SS-64, and produced systems built around the 68008 processor.
While the rapid pace of computer advancement quickly rendered the 68000 obsolete as desktop/workstation CPU, the processor found substantial use in embedded applications. By the early 1980s, quantities of 68000 CPUs could be purchased for less than $30 USD per part. Video game manufacturers used the 68000 as the backbone of many arcade games and home game consoles: Atari's Food Fight, from 1982, was one of the first 68000-based arcade games. Others included Sega's System 16, Capcom's CP System and CPS-2, and SNK's Neo Geo. By the late 1980s, the 68000 was inexpensive enough to power home game consoles, such as Sega's Mega Drive (Genesis) console. The 1993 multi-processor Atari Jaguar console used a 68000 as a support chip, although some developers used it as the primary processor due to familiarity. The 1994 multi-processor Sega Saturn console used the 68000 as a sound co-processor (much as the Mega Drive/Genesis use the Z80 as a sound co-processor).
The 68000 also saw great success as an embedded controller. As early as 1981, laser printers such as the Imagen Imprint-10 were controlled by external boards equipped with the 68000. The first HP LaserJet—introduced in 1984—came with a built-in 8 MHz 68000. Other printer manufacturers adopted the 68000, including Apple with its introduction of the LaserWriter in 1985, the first PostScript laser printer. The 68000 continued to be widely used in printers throughout the rest of the 1980s, persisting well into the 1990s in low-end printers.
The 68000 also saw success in the field of industrial control systems. Among the systems which benefited from having a 68000 or derivative as their microprocessor were families of Programmable Logic Controllers (PLCs) manufactured by Allen-Bradley, Texas Instruments and subsequently, following the acquisition of that division of TI, by Siemens. Users of such systems do not accept product obsolescence at the same rate as domestic users and it is entirely likely that despite having been installed over 20 years ago, many 68000-based controllers will continue in reliable service well into the 21st century.
The 683XX microcontrollers, based on the 68000-architecture, are used in networking and telecom equipment, television set-top boxes, laboratory and medical instruments, and even handheld calculators. The MC68302 and its derivatives have been used in many telecom products from Cisco, 3com, Ascend, Marconi, Cyclades and others. Past models of the Palm PDAs and the Handspring Visor used the DragonBall, a derivative of the 68000. AlphaSmart uses the DragonBall family in later versions of its portable word processors. Texas Instruments uses the 68000 in its high-end graphing calculators, the TI-89 and TI-92 series and Voyage 200. Early versions of these used a specialized microcontroller with a static 68EC000 core; later versions use a standard MC68SEC000 processor.
A modified version of the 68000 formed the basis of the IBM XT/370 Hardware emulator of a System 370 processor.
Architecture
Address bus
The 68000 has a 24-bit external address bus and two byte-select signals "replaced" A0. These 24 lines can therefore reach 16 MB of physical memory with byte resolution. Address storage and computation uses 32 bits internally; however, the 8 high-order address bits are ignored due to the physical lack of device pins. This allows it to run software written for a logically flat 32-bit address space, while accessing only a 24-bit physical address space. Motorola's intent[citation needed] with the internal 32-bit address space was forward compatibility, making it feasible to write 68000 software that would take full advantage of later 32-bit implementations of the 68000 instruction set.
However, this did not prevent programmers from writing forward incompatible software. "24-bit" software that discarded the upper address byte, or used it for purposes other than addressing, could fail on 32-bit 68000 implementations. For example, early (pre-7.0) versions of Apple's Mac OS used the high byte of memory-block master pointers to hold flags such as locked and purgeable. Later versions of the OS moved the flags to a nearby location, and Apple began shipping computers which had "32-bit clean" ROMs beginning with the release of the 1989 Mac IIci.
Internal registers
The CPU has eight 32-bit general-purpose data registers (D0-D7), and eight address registers (A0-A7). The last address register is the stack pointer, and assemblers accept the label SP as equivalent to A7. This was a good number of registers in many ways. It was small enough to allow the 68000 to respond quickly to interrupts (even in the worst case where all 8 data registers D0–D7 and 7 address registers A0–A6 have to be saved, 15 registers in total), and yet large enough to make most calculations fast, because they can be done entirely within the processor without keeping any partial results in memory. (Note that an exception routine in supervisor mode can also save the user stack pointer A7, which would total 8 address registers. However, the dual stack pointer (A7 and A7') design of the 68000 makes this normally unnecessary, except when a task switch is performed in a multitasking system.)
Having two types of registers was mildly annoying at times, but not hard to use in practice. Reportedly, it allowed the CPU designers to achieve a higher degree of parallelism, by using an auxiliary execution unit for the address registers.
Integer representation in the 68000 family is big-endian.
Status register
The 68000 comparison, arithmetic, and logic operations sets bit flags in a status register to record their results for use by later conditional jumps. The bit flags are "zero" (Z), "carry" (C), "overflow" (V), "extend" (X), and "negative" (N). The "extend" (X) flag deserves special mention, because it is separate from the carry flag. This permits the extra bit from arithmetic, logic, and shift operations to be separated from the carry for flow-of-control and linkage.
Instruction set
The designers attempted to make the assembly language orthogonal. That is, instructions are divided into operations and address modes, and almost all address modes are available for almost all instructions. There are 56 instructions and a minimum instruction size of 16 bits. Many instructions and addressing modes are longer to include additional address or mode bits.
Privilege levels
The CPU, and later the whole family, implements two levels of privilege. User mode gives access to everything except the interrupt level control. Supervisor privilege gives access to everything. An interrupt always becomes supervisory. The supervisor bit is stored in the status register, and is visible to user programs.
An advantage of this system is that the supervisor level has a separate stack pointer. This permits a multitasking system to use very small stacks for tasks, because the designers do not have to allocate the memory required to hold the stack frames of a maximum stack-up of interrupts.
Interrupts
The CPU recognizes seven interrupt levels. Levels 1 through 7 are strictly prioritized. That is, a higher-numbered interrupt can always interrupt a lower-numbered interrupt. In the status register, a privileged instruction allows one to set the current minimum interrupt level, blocking lower or equal priority interrupts. For example, if the interrupt level in the status register is set to 3, higher levels from 4 to 7 can caused an exception. Level 7 is a level triggered Non-maskable interrupt (NMI). Level 1 can be interrupted by any higher level. Level 0 means no interrupt. The level is stored in the status register, and is visible to user-level programs.
Hardware interrupts are signaled to the CPU using three inputs that encode the highest pending interrupt priority. A separate Encoder is usually required to encode the interrupts, though for systems that do not require more than three hardware interrupts it is possible to connect the interrupt signals directly to the encoded inputs at the cost of additional software complexity. The interrupt controller can be as simple as a 74LS148 priority encoder, or may be part of a VLSI peripheral chip such as the MC68901 Multi-Function Peripheral (used in the Atari ST range of computers), which also provided a UART, timer, and parallel I/O.
The "exception table" (interrupt vector table interrupt vector addresses) is fixed at addresses 0 through 1023, permitting 256 32-bit vectors. The first vector (RESET) consists of 2 vectors, namely the starting stack address, and the starting code address. Vectors 3 through 15 are used to report various errors: bus error, address error, illegal instruction, zero division, CHK and CHK2 vector, privilege violation (to block privilege escalation), and some reserved vectors that became line 1010 emulator, line 1111 emulator, and hardware breakpoint. Vector 24 starts the real interrupts: spurious interrupt (no hardware acknowledgement), and level 1 through level 7 autovectors, then the 16 TRAP vectors, then some more reserved vectors, then the user defined vectors.
Since at a minimum the starting code address vector must always be valid on reset, systems commonly included some nonvolatile memory (e.g. ROM) starting at address zero to contain the vectors and bootstrap code. However, for a general purpose system it is desirable for the operating system to be able to change the vectors at runtime. This was often accomplished by either pointing the vectors in ROM to a jump table in RAM, or through use of bank switching to allow the ROM to be replaced by RAM at runtime.
The 68000 does not meet the Popek and Goldberg virtualization requirements for full processor virtualization because it has a single unprivileged instruction "MOVE from SR", which allows user-mode software read-only access to a small amount of privileged state.
The 68000 is also unable to easily support virtual memory, which requires the ability to trap and recover from a failed memory access. The 68000 does provide a bus error exception which can be used to trap, but it does not save enough processor state to resume the faulted instruction once the operating system has handled the exception. Several companies did succeed in making 68000-based Unix workstations with virtual memory that worked by using two 68000 chips running in parallel on different phased clocks. When the "leading" 68000 encountered a bad memory access, extra hardware would interrupt the "main" 68000 to prevent it from also encountering the bad memory access. This interrupt routine would handle the virtual memory functions and restart the "leading" 68000 in the correct state to continue properly synchronized operation when the "main" 68000 returned from the interrupt.
These problems were fixed in the next major revision of the 68K architecture, with the release of the MC68010. The Bus Error and Address Error exceptions push a large amount of internal state onto the supervisor stack in order to facilitate recovery, and the MOVE from SR instruction was made privileged. A new unprivileged "MOVE from CCR" instruction is provided for use in its place by user mode software; an operating system can trap and emulate user-mode MOVE from SR instructions if desired.
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Die 68000-Familie ist eine sogenannte Zwei-Adress-Maschine, wobei bei den meisten Befehlen eine variable Datenbreite mit .s = {B,W,L} verwendet werden kann (entspricht 8, 16 oder 32 Bit) und für die beiden Quell- und Ziel-Operanden
| Schreibweise | Beschreibung | Beispiel |
|---|---|---|
| Dn | Datenregister direkt | CLR.B D0 |
| An | Adressregister direkt | MOVEA.W A0,A1 |
| (An) | Adressregister indirekt | CLR.B (A0) |
| (An)+ | Adressregister indirekt mit Postinkrement | CLR.B (A0)+ |
| -(An) | Adressregister indirekt mit Predekrement | CLR.B -(A0) |
| d16(An) | Adressregister indirekt mit 16 Bit Offset | CLR.B 255(A0) |
| d8(An,Ri.s) | Adressreg. ind. mit 8 Bit Offset und Indexregister | CLR.B $44(A0,D0.L) |
| d16(PC) | PC-relativ mit 16 Bit Offset | CLR.B 22(PC) |
| d8(PC,Ri.s) | PC relativ mit 8 Bit Offset und Indexreg. | CLR.B 10(PC,A1.W) |
| #xxxxxxxx | Konstante (Immediate) | MOVEQ.L #15,D0 |
| $xxxx | Speicherdirekt mit 16-Bit-Adresse (Absolute Short) | CLR.B $8000 |
| $xxxxxxxx | Speicherdirekt mit 32-Bit-Adresse (Absolute Long) | CLR.B $11008000 |
oder die komplexen MC68020/30/40/60-Adressierungsarten:
| Schreibweise | Beschreibung | Beispiel |
|---|---|---|
| (dis1,An,Ri.s*scl) | Adressreg. indirekt mit 16-/32-Bit Offset | MOVE.B ($12345678,A1,A2.L*2),D0 |
| ([dis1,An],Ri.s*scl,dis2) | Doppelt indirekt mit Post-Index | MOVE.W ([5,A2],D0.W,$23456),D1 |
| ([dis1,An,Ri.s*scl],dis2) | Doppelt indirekt mit Pre-Index | MOVE.W ([5,A2,D0.W],$23456),D1 |
| (dis1,PC,Ri.s*scl) | PC-indirekt mit 16- oder 32-Bit Offset | JSR (WEITER,PC) |
| ([dis1,PC],Ri.s*scl,dis2) | PC-relativ,doppelt ind m. Post-Index | JSR ([SPRUNG,PC],D1,2) |
| ([dis1,PC,Ri.s*scl],dis2) | PC-relativ,doppelt ind. m. Pre-Index | MOVE.L ([PARAMETER,PC,D1.W],4),D1 |
Der 68000 hat nur eine 16-Bit-ALU und auch einen 16-Bit-Befehlssatz, der aber sowohl mit 8-, 16- als auch 32-Bit-Datentypen umgehen kann (32-Bit-Architektur). Der MC68020/030/040/060 dagegen hat eine 32-Bit-ALU.
Beispiel für ein typisches M68000 Kommando:
JSR
Befehlsformat 0100 1110 10mm mrrr
Das Kommando (Opcode) ist 16 Bit breit. Drei Bits (m) werden für den Adressierungsmodus verwendet, drei weitere Bits für das benutzte (r) Register bzw. eine Distanzadresse (displacement).
0100 1110 1011 1010 wird so zu JSR (d16,PC). Da hier die PC-relative Adressierung mit Distanzadresse (displacement) zur Anwendung kommt, wird das folgende Wort als vorzeichenbehaftete relative Adresse (displacement) verwendet. Andere Kommandos wie MOVEQ #n,Dx sind sogar vollständig in 16 Bit kodiert.
Die Fähigkeit des 68000, bei fast allen Kommandos auch 32 Bit breite Adressen und Daten anzugeben (die dann natürlich bei einem 16-Bit-Bus in mehreren Zyklen gelesen werden mussten), vereinfachte die Softwareentwicklung ungemein, da es sich quasi um eine 32-Bit-Architektur handelte.
Es ergeben sich nicht wie z. B. beim Intel 8086 Probleme, Datensätze über 64 KiB Größe zu adressieren. Wegen der 16-Bit-ALU und des 16-Bit-Datenbusses wird der 68000 oft 16-Bit-Prozessor genannt, er führt jedoch klaglos 32-Bit-Software aus. Wegen der 16-Bit-ALU kostet z. B. eine 32-Bit-Addition die doppelte Zeit. Der Schaltkreis zur Generierung von Adressen hat jedoch volle 32 Bit, so dass z. B. das Durchsuchen eines Textes mit 8 Bit breiten Zeichen nicht langsamer ist, als von einem reinen 16-Bitter zu erwarten wäre. Zudem kann der Text ohne Modifikation des Programms länger als 64 KiB sein. 68000-Software ist 32-Bit-Software.
Der Inhalt der oberen 8 Bit eines Adressregisters wird vom 68000 beim Speicherzugriff ignoriert. Dadurch ist es möglich, diese Bits frei zu nutzen, beispielsweise für Meta-Informationen zu einem Zeiger (pointer). Bei späteren Prozessor-Generationen aus der 68000-Familie mit 32 Bit externem Adressbus führt dies offensichtlich zu Problemen. Da diese Art der Programmierung aber auf den frühen Macintosh-Rechnern sehr verbreitet war, hatten spätere Macintosh-Versionen mit 68020-Prozessor ohne Memory Management Unit (MMU) einen speziellen Baustein, genannt Address Management Unit (AMU), anstelle der MMU, der die oberen 8 Bit von Adressen optional ausmaskierte, um alte Software in einem 24-Bit-Kompatibilitätsmodus verwenden zu können. Als Prozessor mit Nanocode und Microcode ist der 68000 gewissermaßen auf Hardwareebene durch den Hersteller programmierbar. Das führte zu so interessanten Varianten wie dem 68000-360, der direkt auf dem Chip eine abgespeckte Fassung des IBM-System/360-Befehlssatzes ausführen konnte und für ein kleines 360-Modell von IBM benutzt wurde.
Außerdem ermöglichte dies einen einfachen Weg, um Varianten des Chips zu erzeugen. Die erste davon war der 68008, bei dem nur der Nanocode so verändert wurde, dass der Datenbus nur noch mit 8 Bit Breite angesprochen wurde. Eine weitere Variante war der 68010, der wesentlich besser mit virtuellem Speicher betrieben werden konnte und zudem noch einige Detailverbesserungen aufwies. Ein Ableger des 68010 war der nicht lange verfügbare 68012, der mehr Adressleitungen für größere Speicher (bis zu 2 GiB) zur Verfügung stellte. Später wurden Varianten meist direkt von der ursprünglichen CPU abgeleitet, wie z. B. der 68EC020 vom 68020 (24 statt 32 Adressleitungen) – oder der 68EC040 und der 68LC040 vom 68040 (es fehlten dann entweder die FPU oder die MMU). Ab dem 68020 wurden Schritt für Schritt auch erste 64-Bit-Befehle integriert (für einfache Multiplikationen).
Über drei binär kodierte Interruptleitungen können Interrupts mit sieben unterschiedlichen Prioritäten ausgelöst werden, davon ist die höchste nicht maskierbar. Zusammen mit entsprechenden Peripheriebausteinen sind bis zu 256 vektorisierte Interrupts möglich.
Der Prozessor enthält ferner Steuerleitungen, die signalisieren, ob als Nächstes ein Programmbefehl oder ein Datum geholt wird. Dies ermöglicht zwar den Aufbau von Rechnern mit getrenntem Speicher für Programme und Daten; eine Harvard-Architektur ist aber nicht möglich, da die dazu notwendigen getrennten Busse für Programme und Daten hier nicht vorhanden sind.
Verwendung
Bereits zu Beginn der 1980er Jahre fand die CPU, dank optionaler MMU, ihren Weg in die Unix-Welt. Sie wurde in hohen Stückzahlen in die Workstations von Apollo Computer (Apollo), HP (HP 9000-300) und Sun (Sun-1) oder auch von Digital Equipment Corporation (Vax 100) und SGI verbaut.
Mitte der 1980er Jahre folgten dann Personal- und Home-Computer, der erste war Lisa von Apple, die schon bald vom Macintosh (Mac) abgelöst wurde. Er wurde auch im Commodore Amiga, im Atari ST und Sinclair QL (68008) verbaut.
Ende der 1980er und Anfang der 1990er fand er sich dann in Spielkonsolen wie dem Sega Mega Drive oder dem Neo Geo. Auch in Schachcomputern (wie z. B. im Fidelity Mach IV als 68020 mit 20 MHz und Mephisto Amsterdam als 68000 mit 12 MHz) wurde der Prozessor verwendet.
In Taschenrechnern von Texas Instruments wie dem TI-89 (Titanium), TI-92 (Plus) und Voyage 200 findet er heute noch Anwendung. Im Airbus A320 steuert er den Elevator Aileron Computer (ELAC), der Teil des Flugsteuerungs-Systems ist.
Das Haupteinsatzgebiet des Prozessors waren und sind Steuerungsrechner in der Industrie, meist mit einem Echtzeitbetriebssystem wie OS-9 oder pSOS, Nucleus oder Linux68k, wobei Letzteres kein Echtzeitbetriebssystem im eigentlichen Sinne ist. Dieser Einsatz und die große Verbreitung waren nicht zuletzt dank der guten Interruptarchitektur und in der Kombination mit dem VMEbus möglich. In hoher Stückzahl fand sich dieser Prozessor auch in Laserdruckern. Zusätzlich wurde er auf LAN-Karten (Schneider und Koch) und auf SCSI-Controllern (DPD), aber auch in Modems (Zyxel) verwendet. Auch die Automobilindustrie - vornehmlich (Motor-)Steuergeräte - bevorzugte bis zum Erscheinen des PowerPC den Einsatz der MC683xx-Controller-Familie.
Die Hochleistungsmodelle der 68000-Familie sind der 68040 und 68060 (bis 66 bzw. 75 MHz). Da Apple nach dem 68040 auf PowerPC-CPUs wechselte, wurde der 68060 nur noch in Erweiterungskarten für den Amiga und den Atari Falcon 030 (CT60) sowie für spezielle Anwendungen (z. B. in eingebetteten Systemen wie in BMW-Modellen der 1990er Jahre oder hochleistungsfähigen Schachcomputern) verwendet.
Mittlerweile ist der eigentliche 68000 praktisch verschwunden, wird aber noch in Wahlcomputern der Firma Nedap eingesetzt. Motorola (heute Freescale) fertigt eine Vielzahl von Mikrocontrollern, die vom 68000 abstammen. Die Motorola-Coldfire-Familie (auf 68k basierende Entwicklung) ist weiterhin im Bereich eingebetteter Systeme sehr beliebt und geht bis zum V5 mit 400 MHz, der in HP-Laserdruckern Verwendung findet. Die DragonBall-Ableger wurden in den Einsteigermodellen der Palm PDAs verwendet und sind in einfachen Handys verbreitet.
Ein prominentes Beispiel für ein Coldfire-basiertes (Amiga-inspiriertes) System war die Metabox-1000-SetTopBox, die allerdings nie auf den Markt gekommen ist.
Weitere Komponenten
Die Prozessoren 68020, 68030, 68040 und 68060 hatten bereits Funktionen integriert, die heutzutage als „Novum“ z. B. bei ARM herausgestellt werden. Dazu gehören:
* interne Harvard-Architektur * Branch Caches / Prediction * Barrel-Shifter * Pipelining / Prefetch * User / Supervisor Mode (auch Protected Mode oder Kernel Mode genannt) Andere wesentliche Errungenschaften beziehen sich auf die Embedded Controller (Single-Chip) der M68000-Familie, der M683xx-Familie. Hierzu gehören z. B. der MC68332, MC68360, MC68376. Diese Familie waren wegweisend mit folgenden Funktionen:
* BDM (Background Debug Mode), heute Nexus * Dual Core (wobei die zweite CPU als intelligenter Peripheriecontroller eingesetzt wurde, z. B. beim MC68332 als TPU – Timer Processing Unit oder beim MC68360 als CPM – Communications-Processor-Module bzw. QUICC (Quad Integrated Communication Controller). Dieser Controller erlaubte das Verarbeiten aller möglichen seriellen Protokolle. Dies ist der Vorgänger vom bekannten Power QUICC der Power Architecture Familie.
The Motorola 68000 ("'sixty-eight-thousand'"; also called the Motorola 68K, "sixty-eight-kay") is a 16/32-bit[1] CISC microprocessor core designed and marketed by Motorola Semiconductor Products Sector (now Freescale Semiconductor). Introduced in 1979 with HMOS technology as the first member of the successful 32-bit m68k family of microprocessors, it is generally software forward compatible with the rest of the line despite being limited to a 16-bit wide external bus. After 30 years in production, the 68000 architecture is still in use.
History
The 68000 grew out of the MACSS (Motorola Advanced Computer System on Silicon) project, begun in 1976 to develop an entirely new architecture without backward compatibility. It would be a higher-power sibling complementing the existing 8-bit 6800 line rather than a compatible successor. In the end, the 68000 did retain a bus protocol compatibility mode for existing 6800 peripheral devices, and a version with an 8-bit data bus was produced. However, the designers mainly focused on the future, or forward compatibility, which gave the M68K platform a head start against later 32-bit instruction set architectures. For instance, the CPU registers are 32 bits wide, though few self-contained structures in the processor itself operate on 32 bits at a time. The MACSS team drew heavily on the influence of minicomputer processor design, such as the PDP-11 and VAX systems, which were similarly microcoded.
In the mid 1970s, the 8-bit microprocessor manufacturers raced to introduce the 16-bit generation. National Semiconductor had been first with its IMP-16 and PACE processors in 1973-1975, but these had issues with speed. The Intel 8086 in 1977 quickly gained popularity. The decision to leapfrog the competition and introduce a hybrid 16/32-bit design was necessary, and Motorola turned it into a coherent mission. Arriving late to the 16-bit arena afforded the new processor more transistors (roughly 40 000 active versus 20 000 active in the 8086), 32-bit macroinstructions, and acclaimed general ease of use.
The original MC68000 was fabricated using an HMOS process with a 3.5-micron feature size. Formally introduced in September 1979,[2] Initial samples were released in February 1980, with production chips available over the counter in November.[3] Initial speed grades were 4, 6, and 8 MHz. 10 MHz chips became available during 1981[citation needed], and 12.5 MHz chips by June 1982.[3] The 16.67 MHz "12F" version of the MC68000, the fastest version of the original HMOS chip, was not produced until the late 1980s. Tom Gunter, retired Corporate Vice President at Motorola, is known as the "Father of the 68000."
The 68000 became the dominant CPU for Unix based workstations including Sun workstations and Apollo/Domain workstations, and also was used for mass-market computers such as the Apple Lisa, Macintosh, Amiga, and Atari ST. The 68000 was used in Microsoft Xenix systems as well as a prototype NetWare Unix based Server (after the MC6800 series was not found to be powerful enough and before the move to Intel 8X086 processors). The 68000 was used in the first generation of desktop laser printers including the original Apple Inc. LaserWriter and the HP LaserJet. In 1982, the 68000 received an update to its ISA allowing it to support virtual memory and to conform to the Popek and Goldberg virtualization requirements. The updated chip was called the 68010. A further extended version which exposed 31 bits of the address bus was also produced, in small quantities, as the 68012.
To support lower-cost systems and control applications with smaller memory sizes, Motorola introduced the 8-bit compatible MC68008, also in 1982. This was a 68000 with an 8-bit data bus and a smaller (20 bit) address bus. After 1982, Motorola devoted more attention to the 68020 and 88000 projects.
Second-sourcing
Several other companies were second-source manufacturers of the HMOS 68000. These included Hitachi (HD68000), who shrank the feature size to 2.7-microns for their 12.5 MHz version,[3] Mostek (MK68000), Rockwell (R68000), Signetics (SCN68000), Thomson/SGS-Thomson (originally EF68000 and later TS68000), and Toshiba (TMP68000). Toshiba was also a second-source maker of the CMOS 68HC000 (TMP68HC000).
CMOS versions
The 68HC000, the first CMOS version of the 68000, was designed by Hitachi and jointly introduced in 1985.[4] Motorola's version was called the MC68HC000, while Hitachi's was the HD68HC000. The 68HC000 was eventually offered at speeds of 8-20 MHz. Except for using CMOS circuitry, it behaved identically to the HMOS MC68000, but the change to CMOS greatly reduced its power consumption. The original HMOS MC68000 consumed around 1.35 watts at an ambient temperature of 25 °C, regardless of clock speed, while the MC68HC000 consumed only 0.13 watts at 8 MHz and 0.38 watts at 20 MHz. (Unlike CMOS circuits, HMOS still draws power when idle, so power consumption varies little with clock rate.) Apple selected the 68HC000 for use in the Macintosh Portable.
Motorola replaced the MC68008 with the MC68HC001 in 1990.[5] This chip resembled the 68HC000 in most respects, but its data bus could operate in either 16-bit or 8-bit mode, depending on the value of an input pin at reset. Thus, like the 68008, it could be used in systems with cheaper 8-bit memories.
The later evolution of the 68000 focused on more modern embedded control applications and on-chip peripherals. The 68EC000 chip and SCM68000 core expanded the address bus to 32 bits, removed the M6800 peripheral bus, and excluded the MOVE from SR instruction from user mode programs.[6] In 1996, Motorola updated the standalone core with fully static circuitry drawing only 2 µW in low-power mode, calling it the MC68SEC000.
Motorola ceased production of the HMOS MC68000 and MC68008 in 1996,[8] but its spin-off company, Freescale Semiconductor, is still producing the MC68HC000, MC68HC001, MC68EC000, and MC68SEC000, as well as the MC68302 and MC68306 microcontrollers and later versions of the DragonBall family. The 68000's architectural descendants, the 680x0, CPU32, and Coldfire families, are also still in production.
As a microcontroller core
After being succeeded by "true" 32-bit microprocessors, the 68000 was used as the core of many microcontrollers. In 1989, Motorola introduced the MC68302 communications processor.
Applications
At its introduction, the 68000 was first used in high-priced systems, including multiuser microcomputers like the WICAT 150 [3], early Alpha Microsystems computers, Sage II / IV, Tandy TRS-80 Model 16, and Fortune 32:16; single-user workstations such as Hewlett-Packard's HP 9000 Series 200 systems, the first Apollo/Domain systems, Sun Microsystems' Sun-1, and the Corvus Concept; and graphics terminals like Digital Equipment Corporation's VAXstation 100 and Silicon Graphics' IRIS 1000 and 1200. Unix systems rapidly moved to the more capable later generations of the 68k line, which remained popular in that market throughout the 1980s.
By the mid-1980s, falling production cost made the 68000 viable for use in personal and home computers, starting with the Apple Lisa and Macintosh, and followed by the Commodore Amiga, Atari ST, and Sharp X68000. The 68008, on the other hand, was only used in a few home computer systems. The Sinclair QL (though the QL was a sister machine to the ICL One Per Desk, which also used a 68008) was the most commercially important. Helix Systems (in Missouri, United States) designed an extension to the SWTPC SS-50 bus, the SS-64, and produced systems built around the 68008 processor.
While the rapid pace of computer advancement quickly rendered the 68000 obsolete as desktop/workstation CPU, the processor found substantial use in embedded applications. By the early 1980s, quantities of 68000 CPUs could be purchased for less than $30 USD per part. Video game manufacturers used the 68000 as the backbone of many arcade games and home game consoles: Atari's Food Fight, from 1982, was one of the first 68000-based arcade games. Others included Sega's System 16, Capcom's CP System and CPS-2, and SNK's Neo Geo. By the late 1980s, the 68000 was inexpensive enough to power home game consoles, such as Sega's Mega Drive (Genesis) console. The 1993 multi-processor Atari Jaguar console used a 68000 as a support chip, although some developers used it as the primary processor due to familiarity. The 1994 multi-processor Sega Saturn console used the 68000 as a sound co-processor (much as the Mega Drive/Genesis use the Z80 as a sound co-processor).
The 68000 also saw great success as an embedded controller. As early as 1981, laser printers such as the Imagen Imprint-10 were controlled by external boards equipped with the 68000. The first HP LaserJet—introduced in 1984—came with a built-in 8 MHz 68000. Other printer manufacturers adopted the 68000, including Apple with its introduction of the LaserWriter in 1985, the first PostScript laser printer. The 68000 continued to be widely used in printers throughout the rest of the 1980s, persisting well into the 1990s in low-end printers.
The 68000 also saw success in the field of industrial control systems. Among the systems which benefited from having a 68000 or derivative as their microprocessor were families of Programmable Logic Controllers (PLCs) manufactured by Allen-Bradley, Texas Instruments and subsequently, following the acquisition of that division of TI, by Siemens. Users of such systems do not accept product obsolescence at the same rate as domestic users and it is entirely likely that despite having been installed over 20 years ago, many 68000-based controllers will continue in reliable service well into the 21st century.
The 683XX microcontrollers, based on the 68000-architecture, are used in networking and telecom equipment, television set-top boxes, laboratory and medical instruments, and even handheld calculators. The MC68302 and its derivatives have been used in many telecom products from Cisco, 3com, Ascend, Marconi, Cyclades and others. Past models of the Palm PDAs and the Handspring Visor used the DragonBall, a derivative of the 68000. AlphaSmart uses the DragonBall family in later versions of its portable word processors. Texas Instruments uses the 68000 in its high-end graphing calculators, the TI-89 and TI-92 series and Voyage 200. Early versions of these used a specialized microcontroller with a static 68EC000 core; later versions use a standard MC68SEC000 processor.
A modified version of the 68000 formed the basis of the IBM XT/370 Hardware emulator of a System 370 processor.
Architecture
Address bus
The 68000 has a 24-bit external address bus and two byte-select signals "replaced" A0. These 24 lines can therefore reach 16 MB of physical memory with byte resolution. Address storage and computation uses 32 bits internally; however, the 8 high-order address bits are ignored due to the physical lack of device pins. This allows it to run software written for a logically flat 32-bit address space, while accessing only a 24-bit physical address space. Motorola's intent[citation needed] with the internal 32-bit address space was forward compatibility, making it feasible to write 68000 software that would take full advantage of later 32-bit implementations of the 68000 instruction set.
However, this did not prevent programmers from writing forward incompatible software. "24-bit" software that discarded the upper address byte, or used it for purposes other than addressing, could fail on 32-bit 68000 implementations. For example, early (pre-7.0) versions of Apple's Mac OS used the high byte of memory-block master pointers to hold flags such as locked and purgeable. Later versions of the OS moved the flags to a nearby location, and Apple began shipping computers which had "32-bit clean" ROMs beginning with the release of the 1989 Mac IIci.
Internal registers
The CPU has eight 32-bit general-purpose data registers (D0-D7), and eight address registers (A0-A7). The last address register is the stack pointer, and assemblers accept the label SP as equivalent to A7. This was a good number of registers in many ways. It was small enough to allow the 68000 to respond quickly to interrupts (even in the worst case where all 8 data registers D0–D7 and 7 address registers A0–A6 have to be saved, 15 registers in total), and yet large enough to make most calculations fast, because they can be done entirely within the processor without keeping any partial results in memory. (Note that an exception routine in supervisor mode can also save the user stack pointer A7, which would total 8 address registers. However, the dual stack pointer (A7 and A7') design of the 68000 makes this normally unnecessary, except when a task switch is performed in a multitasking system.)
Having two types of registers was mildly annoying at times, but not hard to use in practice. Reportedly, it allowed the CPU designers to achieve a higher degree of parallelism, by using an auxiliary execution unit for the address registers.
Integer representation in the 68000 family is big-endian.
Status register
The 68000 comparison, arithmetic, and logic operations sets bit flags in a status register to record their results for use by later conditional jumps. The bit flags are "zero" (Z), "carry" (C), "overflow" (V), "extend" (X), and "negative" (N). The "extend" (X) flag deserves special mention, because it is separate from the carry flag. This permits the extra bit from arithmetic, logic, and shift operations to be separated from the carry for flow-of-control and linkage.
Instruction set
The designers attempted to make the assembly language orthogonal. That is, instructions are divided into operations and address modes, and almost all address modes are available for almost all instructions. There are 56 instructions and a minimum instruction size of 16 bits. Many instructions and addressing modes are longer to include additional address or mode bits.
Privilege levels
The CPU, and later the whole family, implements two levels of privilege. User mode gives access to everything except the interrupt level control. Supervisor privilege gives access to everything. An interrupt always becomes supervisory. The supervisor bit is stored in the status register, and is visible to user programs.
An advantage of this system is that the supervisor level has a separate stack pointer. This permits a multitasking system to use very small stacks for tasks, because the designers do not have to allocate the memory required to hold the stack frames of a maximum stack-up of interrupts.
Interrupts
The CPU recognizes seven interrupt levels. Levels 1 through 7 are strictly prioritized. That is, a higher-numbered interrupt can always interrupt a lower-numbered interrupt. In the status register, a privileged instruction allows one to set the current minimum interrupt level, blocking lower or equal priority interrupts. For example, if the interrupt level in the status register is set to 3, higher levels from 4 to 7 can caused an exception. Level 7 is a level triggered Non-maskable interrupt (NMI). Level 1 can be interrupted by any higher level. Level 0 means no interrupt. The level is stored in the status register, and is visible to user-level programs.
Hardware interrupts are signaled to the CPU using three inputs that encode the highest pending interrupt priority. A separate Encoder is usually required to encode the interrupts, though for systems that do not require more than three hardware interrupts it is possible to connect the interrupt signals directly to the encoded inputs at the cost of additional software complexity. The interrupt controller can be as simple as a 74LS148 priority encoder, or may be part of a VLSI peripheral chip such as the MC68901 Multi-Function Peripheral (used in the Atari ST range of computers), which also provided a UART, timer, and parallel I/O.
The "exception table" (interrupt vector table interrupt vector addresses) is fixed at addresses 0 through 1023, permitting 256 32-bit vectors. The first vector (RESET) consists of 2 vectors, namely the starting stack address, and the starting code address. Vectors 3 through 15 are used to report various errors: bus error, address error, illegal instruction, zero division, CHK and CHK2 vector, privilege violation (to block privilege escalation), and some reserved vectors that became line 1010 emulator, line 1111 emulator, and hardware breakpoint. Vector 24 starts the real interrupts: spurious interrupt (no hardware acknowledgement), and level 1 through level 7 autovectors, then the 16 TRAP vectors, then some more reserved vectors, then the user defined vectors.
Since at a minimum the starting code address vector must always be valid on reset, systems commonly included some nonvolatile memory (e.g. ROM) starting at address zero to contain the vectors and bootstrap code. However, for a general purpose system it is desirable for the operating system to be able to change the vectors at runtime. This was often accomplished by either pointing the vectors in ROM to a jump table in RAM, or through use of bank switching to allow the ROM to be replaced by RAM at runtime.
The 68000 does not meet the Popek and Goldberg virtualization requirements for full processor virtualization because it has a single unprivileged instruction "MOVE from SR", which allows user-mode software read-only access to a small amount of privileged state.
The 68000 is also unable to easily support virtual memory, which requires the ability to trap and recover from a failed memory access. The 68000 does provide a bus error exception which can be used to trap, but it does not save enough processor state to resume the faulted instruction once the operating system has handled the exception. Several companies did succeed in making 68000-based Unix workstations with virtual memory that worked by using two 68000 chips running in parallel on different phased clocks. When the "leading" 68000 encountered a bad memory access, extra hardware would interrupt the "main" 68000 to prevent it from also encountering the bad memory access. This interrupt routine would handle the virtual memory functions and restart the "leading" 68000 in the correct state to continue properly synchronized operation when the "main" 68000 returned from the interrupt.
These problems were fixed in the next major revision of the 68K architecture, with the release of the MC68010. The Bus Error and Address Error exceptions push a large amount of internal state onto the supervisor stack in order to facilitate recovery, and the MOVE from SR instruction was made privileged. A new unprivileged "MOVE from CCR" instruction is provided for use in its place by user mode software; an operating system can trap and emulate user-mode MOVE from SR instructions if desired.
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