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Full Technical Specifications --> SL7PU (Intel Pentium 4 530J)
| General information | |
| Type | CPU / Microprocessor |
| Family | Intel Pentium 4 |
| Processor number ? | 530J |
| Part number | JM80547PG0801M BX80547PG3000EJ BX80547PG3000ET |
| Frequency (GHz) ? | 3 |
| Bus speed (MHz) ? | 800 |
| Clock multiplier ? | 15 |
| Package type | 775-land FC-LGA4 |
| Socket type | Socket 775 (LGA775) |
| Architecture / Microarchitecture / Other | |
| CPUID | 0F41h |
| Core stepping | E0 |
| Qualification sample | Q09X |
| Previous stepping | SL7J6 |
| Processor core | Prescott |
| Manufacturing technology (micron) | 0.09 |
| L2 cache size (MB) ? | 1 |
| Features | Execute disable bit ? Hyper-Threading technology |
| Core voltage (V) ? | 1.287 - 1.4 |
| Case temperature (°C) ? | 67.7 |
| Intel Pentium 4 530J SL7PU | |||||||||
|---|---|---|---|---|---|---|---|---|---|
|
| ||||||||
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Pentium(R) 4 CPU 3.00GHz |
| Cores: | 1 |
| Logical processors: | 2 |
| Processor type: | Original OEM Processor |
| CPUID signature: | F41 |
| Family: | 15 (0Fh) |
| Model: | 4 (04h) |
| Stepping: | 1 (01h) |
| TLB/Cache details: | Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 entries No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache |
| Cache: | L1 data | L1 instruction | L2 |
|---|---|---|---|
| Size: | 16 KB | 12K uops | 1 MB |
| Associativity: | 8-way set associative | 8-way set associative | 8-way set associative |
| Line size: | 64 bytes | 64 bytes | |
| Comments: | Direct-mapped | Non-inclusive Direct-mapped |
| Instruction set extensions | Additional instructions | ||
|---|---|---|---|
| MMX | CLFLUSH | ||
| SSE | CMOV | ||
| SSE2 | CMPXCHG8B | ||
| SSE3 | FXSAVE/FXRSTORE | ||
| MONITOR/MWAIT | |||
| SYSENTER/SYSEXIT |
| Major features | Other features | ||
|---|---|---|---|
| On-chip Floating Point Unit | 36-bit page-size extensions | ||
| NX bit/XD-bit | 64-bit debug store | ||
| Hyper-Threading Technology | Advanced programmable interrupt controller | ||
| CPL qualified debug store | |||
| Debug store | |||
| Debugging extensions | |||
| L1 context ID | |||
| Machine check architecture | |||
| Machine check exception | |||
| Memory-type range registers | |||
| Model-specific registers | |||
| Page attribute table | |||
| Page global extension | |||
| Page-size extensions (4MB pages) | |||
| Pending break enable | |||
| Physical address extensions | |||
| Self-snoop | |||
| Thermal monitor | |||
| Thermal monitor and software controlled clock facilities | |||
| Time stamp counter | |||
| Virtual 8086-mode enhancements | |||
| xTPR Update Control |