OpenEP4CE6-C is an FPGA development board that consists of the mother board DVK601 and the FPGA core board CoreEP4CE6.
OpenEP4CE6-C supports further expansion with various optional accessory boards for specific application. The modular and open design makes it the ideal for starting application development with ALTERA Cyclone IV series FPGA devices. OpenEP4CE6-C enables you to start your design with the Nios II processor easily and quickly.
All the I/O interfaces above:
For jumpers 16-18:
The DVK601 supports a wide range of different core boards, therefore, some of the interfaces may be Not-Connected and useless while connecting to certain core board. For instance, while connecting to Core3S250E, the '④ 8I/Os_3' and '⑤ 8I/Os_4' are Not-Connected.
Note: The OpenEP4CE6-C does NOT integrate any programming/debugging function, a programmer/debugger is required.
The OpenEP4CE6-C FPGA development board comes with various examples codes for the supported peripherals, which give you a quick start to develop your own application.
Peripheral | Description | Interface | Verilog | VHDL | NIOS II C |
---|---|---|---|---|---|
S29GL128P | NorFLASH | 32I/Os | Y | ||
AT24CXX | EEPROM | I2C | √ | √ | √ |
FM24CXX | FRAM | I2C | √ | √ | √ |
AT45DBXX | DATAFLASH | SPI | √ | ||
SD card | FLASH | SPI | √ | ||
H57V1262GTR | SDRAM | parallel | √ | ||
PCF8563 | RTC | I2C | √ | ||
DS18B20 | Temperature sensor | 1-WIRE | √ | √ | √ |
SP3232 | Serial communication | UART | √ | √ | √ |
SP3485 | Serial communication | UART | √ | √ | √ |
PL2303 | USB TO UART | UART | √ | √ | √ |
FT245 | USB TO FIFO | parallel | √ | ||
CY7C68013A | USB DEVICE | I/Os | √ | ||
ENC28J60 | Ethernet controller | SPI | √ | ||
Buzzer | Sound device | 1I/O (PWM) | √ | √ | √ |
PS/2 keyboard | Input device | PS/2 | √ | √ | |
Single buttons | Input device | ---- | √ | √ | √ |
4x4 keypad | Input device | 8I/Os | √ | √ | √ |
Joystick | Input device | 5I/Os | √ | √ | √ |
LED | Display device | ---- | √ | √ | √ |
8 SEG LED | Display device | 13I/Os | √ | √ | √ |
VGA monitor | Display device | VGA | √ | √ | |
Character LCD | Display device | 11I/Os | √ | √ | |
Graphic LCD | Display device | 11I/Os | √ | ||
3.2 inch multi-color LCD + touch screen | Display device + Input device | 32I/Os | √ |
The OpenEP4CE6-C FPGA development board integrates JTAG interface for programming/debugging.
Pin | Signal Name | Description |
---|---|---|
1 | TCK | Clock signal |
2 | GND | Signal ground |
3 | TDO | Data from device |
4 | VCC(TRGT) | Target power supply |
5 | TMS | JTAG state machine control |
6 | NC | No connect |
7 | NC | No connect |
8 | NC | No connect |
9 | TDI | Data to device |
10 | GND | Signal ground |
The User Guide CD includes development resources listed as follow:
Wiki: www.waveshare.com/wiki/OpenEP4CE6-C
The "Standard Package" and "Accessory Boards Package" below are included.
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