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Full Technical Specifications --> SL7C5 (Intel Celeron D 325)
| General information | |
| Type | CPU / Microprocessor |
| Family | Intel Celeron D |
| Processor number ? | 325 |
| Part number | RK80546RE061256 |
| Frequency (GHz) ? | 2.533 |
| Bus speed (MHz) ? | 533 |
| Clock multiplier ? | 19 |
| Package type | 478-pin FC-mPGA4 |
| Socket type | Socket 478 (mPGA478B) |
| Architecture / Microarchitecture / Other | |
| CPUID | 0F33h |
| Core stepping | C0 |
| Processor core | Prescott-256 |
| Manufacturing technology (micron) | 0.09 |
| Number of cores | 1 |
| L2 cache size (KB) ? | 256 |
| Features | MMX SSE SSE2 SSE3 |
| Core voltage (V) ? | 1.25 - 1.4 |
| Case temperature (°C) ? | 67 |
| Package revision | 02 |
| Intel Celeron D 2.53 GHz SL7C5 | |||||||||
|---|---|---|---|---|---|---|---|---|---|
|
| ||||||||
| General information | |
|---|---|
| Vendor: | GenuineIntel |
| Processor name (BIOS): | Intel(R) Celeron(R) CPU 2.53GHz |
| Cores: | 1 |
| Logical processors: | 1 |
| Processor type: | Original OEM Processor |
| CPUID signature: | F33 |
| Family: | 15 (0Fh) |
| Model: | 3 (03h) |
| Stepping: | 3 (03h) |
| TLB/Cache details: | Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache |
| Cache: | L1 data | L1 instruction | L2 |
|---|---|---|---|
| Size: | 16 KB | 12K uops | 256 KB |
| Associativity: | 8-way set associative | 8-way set associative | 4-way set associative |
| Line size: | 64 bytes | 64 bytes | |
| Comments: | Direct-mapped | Non-inclusive Direct-mapped |
| Instruction set extensions | Additional instructions | ||
|---|---|---|---|
| MMX | CLFLUSH | ||
| SSE | CMOV | ||
| SSE2 | CMPXCHG8B | ||
| SSE3 | FXSAVE/FXRSTORE | ||
| MONITOR/MWAIT | |||
| SYSENTER/SYSEXIT | |||
| Major features | Other features | ||
| On-chip Floating Point Unit | 36-bit page-size extensions | ||
| 64-bit debug store | |||
| Advanced programmable interrupt controller | |||
| CPL qualified debug store | |||
| Debug store | |||
| Debugging extensions | |||
| L1 context ID | |||
| Machine check architecture | |||
| Machine check exception | |||
| Memory-type range registers | |||
| Model-specific registers | |||
| Page attribute table | |||
| Page global extension | |||
| Page-size extensions (4MB pages) | |||
| Pending break enable | |||
| Physical address extensions | |||
| Self-snoop | |||
| Thermal monitor | |||
| Thermal monitor and software controlled clock facilities | |||
| Time stamp counter | |||
| Virtual 8086-mode enhancements | |||