Network -On-Chip (NOC) Design Using FPGA Technology

Network -On-Chip (NOC) Design Using FPGA Technology

Manish Jain

Autore: Manish Jain
Formato: Copertina flessibile
Pagine: 76
Data Pubblicazione: 2019-12-19
Edizione: 1
Lingua: English

Descrizione:
NoC is new paradigm for Systemonchip (SoC) design. NoC based system accommodate multiple asynchronous clocking that many of todays complex SoC design use.The NoC solutions bring a Networking method onchip communication and claim roughly a performance increases over conventional bus system. As a systematic approach, NetworkonChip (NoC) called also NetworkonSilicon, proposes networks as a scalable, reusable and global communication architecture to overcome the pains of future SystemonChip.The idea of NoC is derived from largescale computer networks and distributed computing. However, the routing techniques for NoC have some unique design considerations besides low latency and high throughput. Due to tight constraints on memory and computing resources, the routing techniques for NoC should be reasonably simple. Several switch architectures have been developed for NoC employing XY output selection and wormhole routing.NoC is a layered approach for onchip communication design proposed in literature to cope with issues of current SoC architectures. A scalable communication infrastructure that better supports the trend of SoC integration consists of an onchip packetswit.