Autore: Monobrata Debnath,Junghee Lee
Formato: Copertina flessibile
Pagine: 116
Data Pubblicazione: 2019-01-10
Edizione: 1
Lingua: English
Descrizione:
Rapid innovations in circuit integration technology have successfully integrated billions of transistors on a single chip. The advancement in IC technology has put the challenge of extracting the maximum performance gain from additional resources. In recent times, computer architects have exhorted manycore design to meet next generation computation needs. Chips, equipped with a large number of cores, bracing dynamic parallelism and modest power usage are proposed to meet future computation needs. Intriguingly, the performance of the manycore architecture greatly relies on the competence of the onchip interconnection network. NetworksonChip (NoCs) has emerged as the backbone of manycore architectures. Nevertheless, poor network performance due to congestion could become a major hindrance in the future multicore designs. In the present research, we investigate the causes of congestion in NoCs and facilitate ways to mitigate the performance threat. In particular, the focus of this research is on providing costeffective congestion management solutions suitable for NoCs.