VLSI 87 is the fourth in a series of bi-annual international conferences on Very Large Scale Integration. The biggest change has occurred in the area of computer-aided design tools. The central role of CAD is reflected in the theme for this year's conference: ``Matching Technology and Architecture with the Help of Computer Aided Design'', as well as by the submitted papers. A key concern was to maintain representation throughout the range of disciplines related to the field of VLSI (fabrication technology, circuit design, system architecture, and CAD tools), and also to ensure that the conference remains relevant to both the industrial and academic community. A group of experienced people with special knowledge in different technologies that might be crucial for the future of VLSI were brought together to ensure that the session on technology should be of relevance to CAD tool builders and system architects.
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1987
IFIP TC 10/WG 10.5 International Conference on
Very Large Scale Integration
Vancouver, Canada, 10-12 August 1987
VLSI 87
VLSI Design of Digital Systems
Proceedings of the IFIP TC 10/WG 10.5 International Conference on
Very Large Scale Integration
Vancouver, Canada, 10-12 August 1987
edited by
Carlo H. SÉQUIN
University of California
Berkeley, CA
U.S.A.
PREFACE
VLSI - The Last 10 Years - The Next 10 Years
VLSI'87 is the fourth in a series of bi-annual international conferences on Very
Large Scale Integration. All but the first one have been organized by the working
group WG 10.5 (VLSI), of the IFIP Technical Committee TC 10. Good VLSI systems
result from an intergration of expertise in fabrication technology, circuit design,
system architecture, and CAD tools. Thus a key concern of this working group and
of the conference organizers is to maintain representation throughout the range of
disciplines related to the field of VLSI. We would also like to ensure that this con-
ference remains relevant to both the industrial and academic community.
It is about ten years ago that Lynn Conway and Carver Mead started a "movement"
that rapidly spread through the academic community and eventually also changed
the way of industrial VLSI design. Their computer-science point of view and their
vertically-integrated approach to systems design have shaped the nature of most of
the periodic VLSI conferences. It opened the emerging field of VLSI to a whole
new community of disciples with varied backgrounds. Because of the impact of the
ideas that started to emerge from Xerox PARC in 1977, I set the birth date of VLSI
in that period. This would make VLSI ten years old today! At such round birth-
days it is customary to take stock and look at some of the important developments.
In 1977 the pattern of exponential improvements in technology was already estab-
lished. Exceeding a million transistors on a single silicon chip was just a matter of
time, and the possibility of integrating one billion devices had at least been men-
tioned, even though most people probably were skeptical.
Circuit design remains an ongoing strong activity. This is crucial for the full exploi-
tation of the technological advances. A lot of activity is concentrated on making
ever more dense and effective memory cells or more powerful driver circuits using
combinations of CMOS and bipolar technologies. The success of this year's VLSI
Circuit Symposium in Karuizawa, Japan attests to this fact.
CONTENTS
Preface
Organization
Session 1: KEYNOTE SPEAKERS
Development of Three Dimensional Integration Technologies in Japan
S. Furukawa
European Approaches to Application-Specific Integrated Circuits
J. Borel
System Demands vs. Opportunities
W.R. Heller
Session 2: HIGH-LEVEL SYNTHESIS SYSTEMS
The Role of HDLS in the Digital Design Process
T.L. Thorp (invited speaker) and N.E. Peeling
An RTL Logic Design Aid for Parallel Control VLSI Processors
Y. Nakamura and K. Oguri
Structural Synthesis in the Yorktown Silicon Compiler
R. Camposano
A Knowledge-Based CAD System for Synthesis of Multiprocessor
Digital Signal Processing Chips
J. VanHoof, J. Rabaey and H. DeMan
xiv
Contents
Session 3: SPECIFICATION AND VERIFICATION
Algorithms and Specifications
G. Birtwistle (invited speaker)
Temporal Logic Based, Fast Verification System Using Cover Expressions
H. Nakamura, S. Kono, H. Tanaka and M. Fujita
The Description and Verification of Input Constraints and Input-Output
Specifications of Logic Systems Using a New Extended Regular
Expression
S. Kimura and S. Yajima
Efficient, Stable Algebraic Operations on Logic Expressions
P. McGeer and R. Brayton
Session 4: PLACEMENT AND ROUTING
Top-Down Hierarchical Global Routing by Channelless Gate Arrays
Based on Linear Assignment
U. Lauther
A Gridless Router: Software and Hardware Implementations
K. Suzuki, T. Ohtsuki and M. Sato
Mosaico: An Integrated Macro-Cell Layout System
J. Burns, A. Casotto, M. Igusa, F. Marron, F. Romeo,
A. Sangiovanni-Vincentelli, C. Sechen, H. Shin, G. Srinath and
H. Yaghutiel
Session 5: PLACEMENT REFINEMENT
Use of Triangulation for Global Placement
F. Johannes
Global Spacing of Building-Block Layout
W .- M. Dai and E.S. Kuh
Session 6: HIGH-PERFORMANCE TECHNOLOGIES
High-Performance Bipolar VLSI - The Only Way
G. Wilson (invited speaker)
Contents
Prospects for High Speed Bipolar LSI Technology - Digital Applications
S. Horiguchi (invited speaker), M. Ino and M. Suzuki
GaAs Digital IC's for Computer Applications
M. Rocchi (invited speaker)
CMOS Technology for High Speed VLSI
T. lizuka (invited speaker)
Low Temperature MOS Microelectronics
F. Gaensslen (invited speaker) and R. Jaeger
Session 7: MACHINE ARCHITECTURES
Inference Machines in FGCS Project
S. Uchida (invited speaker)
PEGASUS: A RISC Processor for High-Performance Execution
of Prolog Programs
K. Seo and T. Yokota
Architecture of a 32 Bit Fast Reduced Instruction Set Computer (FRISC)
for Implementation with Advanced Bipolar Differential Logic and
Wafer Scale Hybrid Packaging Technology
H. Greub, J. McDonald and T. Creedon
Session 8: HIGH-SPEED SYSTEMS
A European Program on Wafer Scale Integration
J. Trilhe
Self-Timed Iteration
M. Greenstreet, T. Williams and J. Straunstrup
Functional Simulation for the CRISP Microprocessor
A. Berenbaum and R. Heaton
Session 9: TIMING VERIFICATION AND ELECTRICAL SIMULATION
Simulating MOS VLSI Circuits Using SuperCrystal
R. Bauer, A. Ng, A. Raghunathan, M. Saake and C. Thompson
A Closed-Form Expression for Signal Delay in CMOS-Driven Branched
Transmission Lines
E. Horneber and W. Mathis
Vectorization of the LU-Decomposition for Circuit Simulation
L. Steger
Session 10: LAYOUT SYNTHESIS
Systematic Design of MOS Cells
G. Saucier and G. Thuau
A New Bucketing Technique for Automatic/Interactive Layout Design
M. Edahiro
Synthesizing Transducers from Interface Specifications (or How to get
Chips into Systems)
G. Borriello and R. Katz
Author Index