MC68040RC33 Motorola 68040 33MHz PGA179 CPU FAMILY microprocessors
The MC68040, MC68040V, MC68LC040, MC68EC040, and MC68EC040V (collectively
called M68040) are Motorola’s third generation of M68000-compatible, high-performance,
32-bit microprocessors. All five devices are virtual memory microprocessors employing
multiple concurrent execution units and a highly integrated architecture that provides very
high performance in a monolithic HCMOS device. They integrate an MC68030-compatible
integer unit (IU) and two independent caches. The MC68040, MC68040V, and
MC68LC040 contain dual, independent, demand-paged memory management units
(MMUs) for instruction and data stream accesses and independent, 4-Kbyte instruction
and data caches. The MC68040 contains an MC68881/MC68882-compatible floatingpoint
unit (FPU). The use of multiple independent execution pipelines, multiple internal
buses, and a full internal Harvard architecture, including separate physical caches for both
instruction and data accesses, achieves a high degree of instruction execution parallelism
on all three processors. The on-chip bus snoop logic, which directly supports cache
coherency in multimaster applications, enhances cache functionality.
The M68040 family is user object-code compatible with previous M68000 family members
and is specifically optimized to reduce the execution time of compiler-generated code. All
five processors implement Motorola’s latest HCMOS technology, providing an ideal
balance between speed, power, and physical device size.
called M68040) are Motorola’s third generation of M68000-compatible, high-performance,
32-bit microprocessors. All five devices are virtual memory microprocessors employing
multiple concurrent execution units and a highly integrated architecture that provides very
high performance in a monolithic HCMOS device. They integrate an MC68030-compatible
integer unit (IU) and two independent caches. The MC68040, MC68040V, and
MC68LC040 contain dual, independent, demand-paged memory management units
(MMUs) for instruction and data stream accesses and independent, 4-Kbyte instruction
and data caches. The MC68040 contains an MC68881/MC68882-compatible floatingpoint
unit (FPU). The use of multiple independent execution pipelines, multiple internal
buses, and a full internal Harvard architecture, including separate physical caches for both
instruction and data accesses, achieves a high degree of instruction execution parallelism
on all three processors. The on-chip bus snoop logic, which directly supports cache
coherency in multimaster applications, enhances cache functionality.
The M68040 family is user object-code compatible with previous M68000 family members
and is specifically optimized to reduce the execution time of compiler-generated code. All
five processors implement Motorola’s latest HCMOS technology, providing an ideal
balance between speed, power, and physical device size.
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