High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture 

■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532 

■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices 

Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells 

■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) 

■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)